sunxi: switch PRCM to non-secure on H3/H5 SoCs

The PRCM of H3/H5 SoCs have a secure/non-secure switch, which controls
the access to some clock/power related registers in PRCM.

Current Linux kernel will access the CPUS (AR100) clock in the PRCM
block, so the PRCM should be switched to non-secure.

Add code to switch the PRCM to non-secure.

Signed-off-by: Icenowy Zheng <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Tested-by: Chen-Yu Tsai <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>

diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
index ec5b026ef56a18d803fd8a62219da22721a5d83d..870ff5b1e0983dd2e72a02a7194792cf27b71ed0 100644 (file)
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -66,11 +66,17 @@ void clock_init_sec(void)
 #ifdef CONFIG_MACH_SUNXI_H3_H5
        struct sunxi_ccm_reg * const ccm =
                (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+       struct sunxi_prcm_reg * const prcm =
+               (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
 
        setbits_le32(&ccm->ccu_sec_switch,
                     CCM_SEC_SWITCH_MBUS_NONSEC |
                     CCM_SEC_SWITCH_BUS_NONSEC |
                     CCM_SEC_SWITCH_PLL_NONSEC);
+       setbits_le32(&prcm->prcm_sec_switch,
+                    PRCM_SEC_SWITCH_APB0_CLK_NONSEC |
+                    PRCM_SEC_SWITCH_PLL_CFG_NONSEC |
+                    PRCM_SEC_SWITCH_PWR_GATE_NONSEC);
 #endif
 }